In this technical overview of autonomous vehicles, we share our practical experiences designing autonomous vehicle systems. Autonomous vehicle systems are complex, consisting of three major subsystems: algorithms for localization, perception, and planning and control; client systems, such as the robotics operating system and hardware platform; and the cloud platform, which includes data storage, simulation, high-definition (HD) mapping, and deep learning model training. The algorithm subsystem extracts meaningful information from sensor raw data to understand its environment and make decisions about its actions. The client subsystem integrates these algorithms to meet real-time and reliability requirements. The cloud platform provides offline computing and storage capabilities for autonomous vehicles. Using the cloud platform, we are able to test new algorithms and update the HD map and develop better recognition, tracking, and decision models.

Professor Jean-Luc Gaudiot received the Diplôme d'Ingénieur from the École Supérieure d'Ingénieurs en Electronique et Electrotechnique, Paris, France in 1976 and the M.S. and Ph.D. degrees in Computer Science from the University of California, Los Angeles in 1977 and 1982, respectively. He is currently a Professor in the Electrical Engineering and Computer Science Department at the University of California, Irvine. He was Chair of the Department from 2003 to 2009. During his tenure, the department underwent significant changes. These include the hiring of twelve new faculty members (three senior professors) and the remarkable rise in the US News and World Report® rankings of the Computer Engineering program from 42 to 28 (46 to 36 for the Electrical Engineering program). Prior to joining UCI in January 2002, he was a Professor of Electrical Engineering at the University of Southern California since 1982, where he served as Director of the Computer Engineering Division for three years. He has also designed distributed microprocessor systems at Teledyne Controls, Santa Monica, California (1979-1980) and performed research in innovative architectures at the TRW Technology Research Center, El Segundo, California (1980-1982). He frequently acts as consultant to companies that design high-performance computer architectures, and has served as an expert witness in patent infringement and product liability cases. His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published over 200 journal and conference papers. His research has been sponsored by NSF, DoE, and DARPA, as well as a number of industrial organizations. From 2006 to 2009, he was the first Editor-in-Chief of the IEEE Computer Architecture Letters, a new publication of the IEEE Computer Society, which he helped found to the end of facilitating short, fast turnaround of fundamental ideas in the Computer Architecture domain. From 1999 to 2002, he was the Editor-in-Chief of the IEEE Transactions on Computers. In June 2001, he was elected chair of the IEEE Technical Committee on Computer Architecture, and re-elected in June 2003 for a second two-year term. In 2009, he was elected to the Board of Governors of the IEEE Computer Society for a 3-year-term. He was the Chair of the IEEE Computer Society Publications Board Transactions Operations Committee (2010-2011), the Chair of the IEEE Computer Society Publications Board Magazines Operations Committee in 2012, the IEEE Computer Society vice President, Educational Activities Board in 2013, and 2014-2015 IEEE Computer Society vice President, Publications Board. He is now the 2017 IEEE Computer Society President. Dr. Gaudiot is a member of AAAS, ACM, and IEEE. He has also chaired the IFIP Working Group 10.3 (Concurrent Systems). He was co-General Chairman of the 1992 International Symposium on Computer Architecture, Program Committee Chairman of the 1993 IFIP Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, the 1993 IEEE Symposium on Parallel and Distributed Processing (Systems Track), the 1995 Parallel Architectures and Compilation Techniques Conference (PACT ‘95), the High Performance Computer Architecture conference in 1999 (HPCA-5), and the 2005 International Parallel and Distributed Processing Symposium. In 1999, he became a Fellow of the IEEE, “For Contributions to the Programmability and Reliability of Dataflow Architectures.” He was elevated to the rank of AAAS Fellow in 2007, “For Distinguished Contributions to the Design and Analysis of Highly Efficient Multiprocessor and Memory System Architectures.”

As the next-generation cellular communication technology, 5G New Radio (NR) aims to cover a wide range of service cases, including broadband human-oriented communications, time-sensitive applications with ultra-low latency, and massive connectivity for Internet of Things. With its broad range of operating frequencies, the channel coherence time for NR varies greatly. To address such needs, a number of different OFDM numerologies are defined for NR, allowing a wide range of frequency and time granularities for data transmission. Under this numerology, it is necessary to perform scheduling with a time resolution as small as ~100 µs. This requirement poses a new challenge that does not exist in LTE and cannot be supported by any existing LTE schedulers. In this talk, I will present the design of GPF − a GPU-based proportional fair (PF) scheduler that can meet the ~100 µs time requirement. The key ideas in the design include decomposing the scheduling problem into a large number of small and independent sub-problems and selecting a subset of sub-problems from the most promising search space to fit into a GPU platform. By implementing GPF on an off-the-shelf Nvidia Quadro P6000 GPU, we show that GPF is able to achieve near-optimal performance while meeting the ~100 µs time requirement. GPF represents the first successful design of a GPU-based PF scheduler that can meet the new time requirement in 5G NR.

Tom Hou is the Bradley Distinguished Professor of Electrical and Computer Engineering at Virginia Tech, USA. He received his Ph.D. degree from NYU Tandon School of Engineering (formerly Polytechnic University) in 1998. His current research focuses on developing innovative solutions to complex science and engineering problems arising from wireless and mobile networks. He is particularly interested in exploring new performance limits at the network layer by exploiting advances at the physical layer. In recent years, he has been actively working on cross-layer optimization problems for cognitive radio wireless networks, cooperative communications, MIMO-based networks and energy related problems. He is also interested in wireless security. Prof. Hou was named an IEEE Fellow for contributions to modeling and optimization of wireless networks. He has published two textbooks: Cognitive Radio Communications and Networks: Principles and Practices (Academic Press/Elsevier, 2009) and Applied Optimization Methods for Wireless Networks (Cambridge University Press, 2014). The first book has been selected as one of the Best Readings on Cognitive Radio by the IEEE Communications Society. Prof. Hou′s research was recognized by five best paper awards from the IEEE and two paper awards from the ACM. He holds five U.S. patents.

Prof. Hou is a prominent leader in the research community. He was an Area Editor of IEEE Transaction on Wireless Communications (Wireless Networking area), and an Editor of IEEE Transactions on Mobile Computing, IEEE Journal on Selected Areas in Communications − Cognitive Radio Series, and IEEE Wireless Communications. Currently, he is an Editor of IEEE/ACM Transactions on Networking and ACM Transactions on Sensor Networks. He is the Steering Committee Chair of IEEE INFOCOM conference − the largest and top ranked conference in networking. He is a member of the Board of Governors as well as a Distinguished Lecturer of the IEEE Communications Society.